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PCB cost cutting 'hacks'

Now that component/product miniaturisation appears to have hit a wall, the biggest challenges that I have seen in the past 12 months are those of cost cutting. With board space worries diminishing the main question now is, "How can we make this board as cheaply as possible"? With every major player now having their boards made in the Far East where can they make gains over their competitors? Well it's in the PCB layout.

I was presented with what I thought was a fairly straight-forward design for a consumer product last year, but was then told it had to be done on a single-sided PCB. It's amazing how quickly board space disappears when adding 0R links to jump tracks. However, with meticulous planning and armed with a variety of 0R 'jumper' footprints the improbable can become possible.


The savings in fabrication costs are considerable for a high volume product and are possible for just a few extra days of design effort. The cost of extra 0R parts are nothing compared to extra copper layers on a PCB. Having a good CAD tool like Cadstar that allows easy addition of 0R links, net splitting and effective back-annotation to the schematic makes the logistical side of the task quite painless.

Obviously you wouldn't want a board without a 0V plane for a design with fast signals but the principle is the same. Careful and thoughtful management of power routing, split planes, return paths and solid planes can save you layers, ..and £££s. Just as often as I've seen 0.125mm tracks use for decoupling (urgh!) I have seen huge split planes used for stationary DC voltage supplies of under 500mA. This is wasting valuable space and adding to your expensive layer count.

Conversely, adding extra copper plane layers can reduce the need for expensive heat sinks and cooling methods. Recent tests on some high power boards that I recently designed have shown that extra planes have much more of an effect on cooling than we thought. Another cost cutting 'hack'.

Finally, I have seen a few double-sided SMD boards, even recently, where the decoupling capacitors are placed on the other side to their respective ICs seemingly by default. Not only is this bad design practice but when there is little else on the underside of the board the need for a second reflow process could have been completely avoided with a bit more design effort.

I'm sure that all experienced engineers are well on top of all of these factors, but not all good engineers have the experience yet, especially in younger companies, so it always pays to have an experienced PCB designer on your side.

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